1. Technical Field
The present disclosure relates to a semiconductor power device and to a corresponding manufacturing method. In particular, the disclosure relates to a method of manufacturing a power device comprising column structures for charge balancing, and to the corresponding device.
2. Description of the Related Art
As is known, in the last few years an attempt has been made to increase the efficiency of the aforesaid devices in terms of increase of the breakdown voltage and decrease of the output resistance of the devices themselves.
The U.S. Pat. Nos. 6,586,798, 6,228,719, 6,300,171, and 6,404,010, all filed in the name of the present applicant, describe methods for solving the problems set forth above. In these patents MOS power devices are described, comprising column structures having a first type of conductivity (for example, P), spaced apart by areas of epitaxial layer having a second type of conductivity (here N). Basically, in order to provide the column structures, a sequence of steps of growth of epitaxial layers of an N type is carried out, each step being followed by a step of implantation of dopant of a P type. Stacking of the implanted regions thus forms column structures that represent an extension of the body regions of the device within the epitaxial layer that constitutes the drain region of the device. The concentration of charge of the dopant introduced via the implants, i.e., the concentration of the column structures of a P type thus formed, is equal, but of opposite sign, to the concentration of charge introduced epitaxially. Consequently, thanks to the charge balance thus obtained, it is possible to provide vertical-conduction power devices with high breakdown voltage and low output resistance, due to the high concentration of the epitaxial layer (Multi-drain approach). Moreover, it is also known that by increasing the density of the elementary strips that form the device, i.e., increasingly packing the device itself, it is possible to increase further the concentration of charge of the epitaxial layer, obtaining devices that, given the same breakdown voltage (linked to the height of the columns), have a progressively lower output resistance.
On the other hand, however, in order to increase the density of the elementary strips of the device, it is necessary to reduce the thermal budget of the device and consequently increase the number of the steps of epitaxial growth.
This determines an increase in the cost of the device, in the cycle time, and in the defectiveness created by the various steps of epitaxial growth. In particular, with reference to the latter problem, each defect left at the interface between one epitaxial layer and the next renders the device less efficient.
Moreover, there exist solutions that seek to reach charge balance via formation of trenches and filling of said trenches with successive layers of polysilicon, thermal oxide, deposited oxide. However, also these solutions do not solve the problem of defectiveness.
The approaches that envisage total or partial filling by means of dielectrics incur principally in two problems: defectiveness induced by stresses due to the fact that the dielectric has a coefficient of thermal expansion different from that of the silicon in which it is embedded, and difficulty in obtaining a process of filling that is simple and repeatable in the case where the “aspect ratio” of the trenches (i.e., the ratio between the depth and the width of the trenches) is high. In order to overcome these difficulties, it has been proposed, according to the U.S. Pat. No. 7,944,018, to leave the trenches empty and seal them only at their surface opening so as not to render them accessible from outside the device. This method presents the disadvantage of being difficult to implement in so far as it involves steps of ion implantation within the trenches using a plurality of angles of implantation so as to reach in a uniform way the internal wall of the trenches, and the presence of intermediate steps of filling, albeit temporary, of the trenches. This is due to the fact that the nature of the materials available for surface closing of the trenches is such that, in order to preserve them during all the steps of formation of the device, they can be deposited only during the terminal manufacturing steps.
Other approaches envisage filling of the trenches with epitaxial silicon (U.S. Pat. No. 8,304,311), but present, however, other drawbacks basically due to the relatively long duration of the filling process and/or to the difficulty of repeatability. In fact, in order to prevent closing of the access to the trench before filling thereof has been completed, it is expedient to slow down the process of growth of the epitaxial silicon within the trench. In this way, the duration of the process of filling of the trench increases considerably.
Instead, if the step of filling of the trench is speeded up, micro-voids may form inside the trenches themselves, randomly distributed, thus causing the process to have a low repeatability in terms of control of the charge introduced, with consequent impact on the performance of the devices thus manufactured.